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Monday, March 02, 2009

Gate Drive for step-down switching regulator

Cdv/dt induced turn-on of the synchronous MOSFET deteriorates
performance in synchronous buck regulators. We will discuss this
problem and provide several solutions that can reduce the effects.
An in-circuit waveform showing the Cdv/dt induced
turn-on effect at Q2 gate is demonstrated in Figure 7. The
gate drive circuit might further deteriorate this Cdv/dt
induced turn-on problem. It is clear in Figure 7 that the
gate driver can only pull the gate voltage of Q2 down to
0.7V, instead of zero, when Q2 is turned off. However, the
Cdv/dt induced voltage is sitting on top of this turn-off
gate voltage and makes Q2 more vulnerable to the Cdv/dt
induced turn-on problem. The gate driver used in Figure 7
is created by a bipolar process.


“Shoot-through” in Synchronous Buck Converters

The synchronous buck circuit is in widespread use to
provide “point of use” high current, low voltage
power for CPU’s, chipsets, peripherals etc. In the
synchronous buck converter, the power stage has a
“high-side” (Q1 below) MOSFET to charge the
inductor, and a “Low-side” MOSFET which replaces
a conventional buck regulator’s “catch diode” to
provide a low-loss recirculation path for the inductor

Shoot-through is defined as the condition when both
MOSFETs are either fully or partially turned on,
providing a path for current to “shoot through” from
VIN to GND. To minimize shoot-through,
synchronous buck regulator IC’s employ one of two
techniques to ensure “break before make” operation
of Q1 and Q2 to minimize shoot-through:

1. Fixed “dead-time”: A MOSFET is turned off,
then a fixed delay is provided before the lowside
is turned on. This circuit is simple and
usually effective, but suffers from its lack of
flexibility if a wide range of MOSFET gate
capacitances are to be used with a given
controller. Too long a dead-time means high
conduction losses. Too short a dead time can
cause shoot-through. A fixed dead-time
typically must err on the “too long” side to allow
high CGS MOSFETs to fully discharge before
turning on the complementary MOSFET.

2. Adaptive gate drive: This circuit looks at the
VGS of the MOSFET that’s being driven off to
determine when to turn on the complementary
MOSFET. Theoretically, adaptive gate drives
produce the shortest possible dead-time for a
given MOSFET without producing shootthrough.
In practice, a combination of adaptive and fixed
produces the best results, and is typically what is in
today’s PWM controllers and gate drivers as shown
in Figure 2


A New Hybrid Gate Drive Scheme for High
Frequency Buck Voltage Regulators

This paper presents a new hybrid drive scheme
for a synchronous buck voltage regulator (VR). The
proposed current-source driver is used to drive the control
MOSFET to achieve fast switching speed and reduce the
switching loss significantly due to the parasitic inductance in
addition to gate energy recovery. Conventional voltage
driver is used for synchronous rectifier (SR) MOSFET for
its simplicity and good immunity and alleviation of dv/dt
effect. The experimental results prove the advantages of the
new drive scheme and a significant efficiency improvement
has been achieved. At 1.3 V output, the new driver improves
the efficiency from 82.8% using a conventional driver to
85.6% (an improvement of 2.8%) at 20 A, and at 25 A, from
80.5% to 83.0% (an improvement of 2.5%). The new drive
can also be integrated into a standard drive integrated
circuit (IC) and replace the conventional voltage drive IC
directly. Overall, the new driver scheme is very promising
from the standpoints of both performance and costeffectiveness.

Figure 2 shows the buck converter with the proposed
hybrid drive circuit. The key waveforms are shown in
Figure 3. Essentially, the new high-side current-source
driver is used for the control MOSFET to achieve fast
switching transition. It consists of two driver MOSFETs
S1 and S2, a bipolar transistor pair S3 and S4, the resonant
inductor Lr, the bootstrap capacitor Cf , diode Df and the
blocking capacitor Cb. Vc are the drive voltages. Cgs1 and
Cgs2 are the input gate capacitors of MOSFETs Q1 and Q2
respectively. S1 and S2 are switched out of phase with
complimentary control respectively.

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